MCS-51单片机内部结构
MCS-51即80C51芯片，由一个8位CPU，一个4KBROM和一个128BRAM，2×16T/C，4×8I/O，1个UART，5个INT以及2个64KBBEC组成。
The MCS-51, or 80C51 chip, consists of an 8-bit CPU, a 4KBROM and a 128BRAM, 2×16T/C, 4×8I/O, 1 UART, 5 INTs, and 2 64KBBEC.
CPU介绍
CPU由控制器和运算器组成，控制器由程序计数器PC、数据指针寄存器DPTR组成，用于统一指挥和控制各单元协调工作，从ROM中取出指令进行译码并执行指令；运算器由累加器ACC、程序状态字寄存器PSW组成，用于对数据进行算术运算和逻辑操作，读取计算缓存器内容，结果暂存，修改运行标志。
程序计数器用于引导程序运行，指向ROM存储单元的地址指针，存放着下一条指令的首地址；数据指针寄存器用于引导数据传送，指向ROM或RAM存储单元的地址指针。累加器是存放操作数或中间运算结果的寄存器；程序状态字寄存器存放程序运行过程中的各种状态信息的寄存器，各位都有其特殊意义，状态值可由硬件形成或由指令修改。
Cpu consists of controller and operator, controller consists of program counter PC, data pointer register DPTR, for unified command and control of each unit coordination work, from the ROM to take out instructions for decoding and executing instructions;
The program counter is used to boot the program, pointing to the address pointer of the ROM storage unit, which holds the first address of the next instruction, and the data pointer register is used to boot the data transfer, pointing to the address pointer of the ROM or RAM storage unit. The accumulator is a register that holds the operating number or intermediate operation results, and the program status word register holds the register of various state information in the course of the program operation, each of which has its special meaning, and the state value can be formed by hardware or modified by instruction.
参考资料：百度百科
翻译；谷歌翻译
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文案|李恒宇
排版|李恒宇
审核|李小雪